High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip |
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| Author:
| Wang, Zheng
Chattopadhyay, Anupam |
| Series title: | Computer Architecture and Design Methodologies Ser. |
| ISBN: | 978-981-10-1072-9 |
| Publication Date: | Jul 2017 |
| Publisher: | Springer
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| Book Format: | Hardback |
| List Price: | USD $149.99USD $109.99 |
Book Description:
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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into...
More DescriptionThis book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.